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Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signal | | Jian-Feng Liu
; Lei Zhao
; Jia-Jun Qin
; Yun-Fan Yang
; Li Yu
; Yu Liang
; Shu-Bin Liu
; Qi An
; | | Date: |
14 Jan 2016 | | Abstract: | High precision and large dynamic range measurement are required in the
readout systems for the Water Cherenkov Detector Array (WCDA) in Large High
Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of
12-bit 40 MSPS Analog-to-Digital Converter (ADC) Application Specific
Integrated Circuit (ASIC) designed for the readout of LHAASO WCDA. Combining
this ADC and the front-end ASIC finished in our previous work, high precision
charge measurement can be achieved based on the digital peak detection method.
This ADC is implemented based on power-efficient Successive Approximation
Register (SAR) architecture, which incorporates the key parts such as
Capacitive Digital-to-Analog Converter (CDAC), dynamic comparator and
asynchronous SAR control logic. The simulation results indicate that the
Effective Number Of Bits (ENOB) with a sampling rate of 40 MSPS is better than
10 bits in an input frequency range below 20 MHz, while its core power
consumption is 6.6 mW per channel. The above results are good enough for the
readout requirements of the WCDA. | | Source: | arXiv, 1601.3549 | | Services: | Forum | Review | PDF | Favorites | |
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