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Article overview
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Investigating the Dirac operator evaluation with FPGAs | | G. Korcyl
; P. Korcyl
; | | Date: |
18 Apr 2019 | | Abstract: | In recent years the computational capacity of single Field Programmable Gate
Arrays (FPGA) devices as well as their versatility has increased significantly.
Adding to that the High Level Synthesis frameworks allowing to program such
processors in a high level language like C++, makes modern FPGA devices a
serious candidate as building blocks of a general purpose High Performance
Computing solution. In this contribution we describe benchmarks which we
performed using a Lattice QCD code, a highly compute-demanding HPC academic
code for elementary particle simulations. We benchmark the performance of a
single FPGA device running in two modes: using the external or embedded memory.
We discuss both approaches in detail using the Xilinx U250 device and provide
estimates for the necessary memory throughput and the minimal amount of
resources needed to deliver optimal performance depending on the available
hardware platform. | | Source: | arXiv, 1904.8616 | | Services: | Forum | Review | PDF | Favorites | |
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