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Synthesis of Parallel Synchronous Software | | Pantea Kiaei
; Patrick Schaumont
; | | Date: |
6 May 2020 | | Abstract: | In typical embedded applications, the precise execution time of the program
does not matter, and it is sufficient to meet a real-time deadline. However,
modern applications in information security have become much more
time-sensitive, due to the risk of timing side-channel leakage. The timing of
such programs needs to be data-independent and precise. We describe a parallel
synchronous software model, which executes as N parallel threads on a processor
with word-length N. Each thread is a single-bit synchronous machine with
precise, contention-free timing, while each of the N threads still executes as
an independent machine. The resulting software supports fine-grained parallel
execution. In contrast to earlier work to obtain precise and repeatable timing
in software, our solution does not require modifications to the processor
architecture nor specialized instruction scheduling techniques. In addition,
all threads run in parallel and without contention, which eliminates the
problem of thread scheduling. We use hardware (HDL) semantics to describe a
thread as a single-bit synchronous machine. Using logic synthesis and code
generation, we derive a parallel synchronous implementation of this design. We
illustrate the synchronous parallel programming model with practical examples
from cryptography and other applications with precise timing requirements. | | Source: | arXiv, 2005.2562 | | Services: | Forum | Review | PDF | Favorites | |
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