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06 October 2024 |
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Article overview
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On the Simulation of Hypervisor Instructions for Accurate Timing Simulation of Virtualized Systems | | Swapneel C. Mhatre
; Priya Chandran
; | | Date: |
1 Jun 2022 | | Abstract: | Architectural simulators help in better understanding the behaviour of
existing architectures and the design of new architectures. Virtualization has
regained importance and this has put a pressing demand for the simulation of
virtualized systems. Existing full-system simulators for virtualized systems
simulate the application program instructions and the operating system
instructions but abstract the hypercalls or traps to the hypervisor. This leads
to inaccuracy in the simulation. This paper proposes an approach to simulate
hypervisor instructions in addition to operating system instructions for
accurate timing simulation of virtualized systems. The proposed approach is
demonstrated by simulating RISC-V binary instructions. The simulator is an
execution-driven, functional-first, hardware-based simulator coded in Verilog.
The paper concludes that the proposed approach leads to accurate timing
simulation of virtualized systems. | | Source: | arXiv, 2206.00258 | | Services: | Forum | Review | PDF | Favorites | |
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