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PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques | | Ataberk Olgun
; Juan Gomez Luna
; Konstantinos Kanellopoulos
; Behzad Salami
; Hasan Hassan
; Oguz Ergin
; Onur Mutlu
; | | Date: |
1 Jun 2022 | | Abstract: | DRAM-based main memory is used in nearly all computing systems as a major
component. One way of overcoming the main memory bottleneck is to move
computation near memory, a paradigm known as processing-in-memory (PiM). Recent
PiM techniques provide a promising way to improve the performance and energy
efficiency of existing and future systems at no additional DRAM hardware cost.
We develop the Processing-in-DRAM (PiDRAM) framework, the first flexible,
end-to-end, and open source framework that enables system integration studies
and evaluation of real PiM techniques using real DRAM chips. We demonstrate a
prototype of PiDRAM on an FPGA-based platform (Xilinx ZC706) that implements an
open-source RISC-V system (Rocket Chip). To demonstrate the flexibility and
ease of use of PiDRAM, we implement two PiM techniques: (1) RowClone, an
in-DRAM copy and initialization mechanism (using command sequences proposed by
ComputeDRAM), and (2) D-RaNGe, an in-DRAM true random number generator based on
DRAM activation-latency failures.
Our end-to-end evaluation of RowClone shows up to 14.6X speedup for copy and
12.6X initialization operations over CPU copy (i.e., conventional memcpy) and
initialization (i.e., conventional calloc) operations. Our implementation of
D-RaNGe provides high throughput true random numbers, reaching 8.30 Mb/s
throughput. Over the Verilog and C++ basis provided by PiDRAM, implementing the
required hardware and software components, implementing RowClone end-to-end
takes 198 (565) and implementing D-RaNGe end-to-end takes 190 (78) lines of
Verilog (C++) code. PiDRAM is open sourced on Github:
this https URL | | Source: | arXiv, 2206.00263 | | Services: | Forum | Review | PDF | Favorites | |
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